In state of the art semiconductor device processing, lithography is a key technology in fabricating wafers with large numbers of chip sites. Although x-ray and electron beam lithography tools are useful and effective, especially for mask making, photolithography remains the most widely used lithography tool for semiconductor wafer fabrication. Likewise, although a variety of exposure tools have been developed over the years, step and repeat cameras are ubiquitous in commercial integrated circuit manufacture. These tools, usually referred to as steppers, rely for their effectiveness on the ability to register photomasks in exact alignment from level to level. Typical state of the art wafer fabrication processes have several levels or layers where photomasks are employed in conjunction with standard process steps to define features in the device substrate or on the layers. In the usual process, alignment marks are formed at the first processing level to provide means for registering the photomask for the subsequent photolithography steps. The marks usually consist of a pattern of marks formed by photolithograpic masking and either etching or lift-off. The pattern of marks remain throughout the process.
Photolithographic patterns are typically made by spinning a uniform coating of photoresist over the entire wafer, exposing the photoresist with actinic light directed through a photomask, and developing the photoresist to leave a photoresist pattern.
In this description, the term photomask refers to the master mask or reticle that defines the pattern of actinic radiation incident on the photoresist. The term lithographic mask refers to the patterned photoresist which is used to define the regions where processing activity, e.g. etching, metal deposition, occurs in the layer masked by the photoresist. Each photomask, and the photoresist pattern produced therefrom, typically has imbedded therein a series of alignment marks, which are key ingredients in multilevel wafer fabrication. For example, if the first photoresist pattern is used to mask an oxide layer, silicon layer, or a metal layer for an etch step, the alignment marks will be transferred to the layer as an etched pattern. In this way when each sequential layer is deposited and patterned, the alignment marks from the first layer can be used to register all succeeding photomasks. Thus the desired topography can be constructed with great precision in the x-y planes. In projection lithography systems, the alignment itself is usually performed with automated tools. State of the art steppers have vision systems that easily identify the alignment marks on the wafer and automatically register the next photomask with the alignment marks previously formed, provided that the integrity of the alignment marks is maintained during the process.
The initial alignment mark pattern is frequently made in a metal layer formed at the edge of the wafer for alignment purposes. However, in some processes, notably in III-V semiconductor stack processes, the III-V semiconductor processing is inconsistent with the presence of metal alignment marks. In such cases, it is necessary or desirable to form alignment marks in the semiconductor layers themselves. One such general case is one wherein a feature is defined early in the process, and growth (or regrowth) of other layers follows the patterning of that feature. In this situation, alignment marks formed in the semiconductor layer in conjunction with the first patterning step are covered by at least one later epitaxially grown layer. As a consequence, the marks may be partially or fully obliterated or severely distorted during the growth steps. This is especially likely in processes that use multiple growth or regrowth steps.
Multiple regrowth of epitaxial layers is advantageously used in the manufacture of heterostructure bipolar transistors (HBTs). HBTs are important for optoelectronic integrated circuits, digital ICs, and microwave/millimeter wave low phase-noise oscillators. See D. Caffin et al., Electronics Letters 33, p. 149 (1997); Stanaka et al., Electronics Letters 26, p. 1439 (1990). InGaAs/InP HBTs are of increasing importance since these devices offer the advantages, over GaAs/AlGaAs HBTs, of a lower turn-on voltage, higher electron mobility, better thermal dissipation, and better microwave performance. See D. Caffin et al., IEEE TRansactions on Electron Devices, 44, p. 930 (1997); S. Yamahata et al., IEEE GaAs IC Symposium, p. 345 (1994). An optimum double heterostructure bipolar transistor (DHBT) layer structure can be employed to take advantage of these superior material properties. To increase the bandwidth of the device, the dimensions of the device should be scaled down. See B. Agarwal et al., IEDM, p. 743 (1997). Vertical scaling increases the unity current gain cutoff frequency, f.sub.t, of the device since f.sub.t, scales as 1/(2.pi.t.sub.eff), where the effective transit time, t.sub.eff, is dominated by the base-collector transit time, t.sub.b. On the other hand, lateral device scaling is required to improve the maximum available power gain, f.sub.max, of the device, since it scales as (f.sub.t /8.pi.R.sub.b C.sub.bc).sup.1/2, where R.sub.b is the base resistance and C.sub.bc is the base-collector capacitance. Defining the subcollector prior to growing the active HBT stack offers the advantage of lateral scaling.
Several techniques have been developed to reduce parasitics, such as C.sub.bc. They include improvements in device processing, as well as epitaxial regrowth. One processing technique, for example, uses implant isolation under the base contact for lateral scaling of GaAs-based HBTs. See M-C Ho et al., IEEE Electron Device Lett. 16 (11), p. 512 (1995); M. Yanagihara et al., Solid-State Electronics 41 (10), p. 1615 (1997); P. Asbeck, Solid-State Electronics 38 (9), p. 1691 (1995). This results in a highly resistive layer under the external base of the structure, which reduces C.sub.bc. Implant isolation may also be used for device isolation in the GaAs material system. See F. Ren et al., Solid-State Electronics 38 (9), p. 1635 (1995). However, InP/InGaAs devices cannot be isolated this way since implantation does not produce sufficient resistivity in this system for isolation. Other techniques to reduce C.sub.bc have also been developed, including planarization with nitride or polyimide, polycrystal isolation using SiO.sub.2, micro-airbridge isolation, and selective undercut of the collector. See B. Willen et al., Electronic Letters 33 (8), p. 719 (1997); H. Shin et al., IEEE Electron Device Lett. 19 (8), p. 297 (1998); K. Mochizuki et al., IEEE Electron Device Lett. 19 (2), p. 47 (1998); T. Oka et al., IEEE Electron Device Lett. 18 (4), p. 154 (1997); S. Tadayon et al., Electronics Letters 29, p. 26 (1993); W. L. Chen et al., IEEE Electron Device Lett. 18 (7), p. 355 (1997); R.F. Kopf et al., Solid-State Electronics 42 (12), p. 2239 (1998). These techniques require fabricating devices using mesa isolation and reducing lateral confinement of the collector region by selectively undercutting this region and either back-filling the gap with dielectric material or leaving it open to air. Since these InP/InGaAs HBTs are fabricated using a double mesa structure, the base-collector junction area is substantially larger than the emitter area to accommodate the base electrode pad. Unfortunately, the collector region may only be undercut a small amount, on the order of 1 to 2 .mu.m and also maintain good device characteristics and reliability. For example, the mesa structure may is crack off or collapse, and create base-collector shorts, if it is undercut too much. To avoid problems with extensive mesa undercutting, while also reducing C.sub.bc further, a transferred substrate technique has been developed. See B. Agarwal et al., IEDM, p. 743 (1997). This may also be termed active packaging, where certain fabrication steps are performed after the partially processed device is packaged or transferred onto a host platform. See Luryi et al., IEEE Transactions on Electron Devices 41 (12), p. 2241 (1994). This technique is a flip-chip process with narrow and aligned emitter and collector stripes on opposite sides of the base epitaxial layer. With this technique, a very high f.sub.max has been obtained. This technique requires some complex processing, such as lithography, etching, and metallization, on opposite sides of the epitaxial base layer.
Multistep epitaxial regrowth offers some advantages over the above processing techniques since the final processing does not involve any extensive undercutting or flip-chip processing. Several growth techniques, including molecular beam epitaxy (MBE), gas-source molecular beam epitaxy (GSMBE), metal-organic chemical vapor deposition (MOCVD), and metal-organic molecular beam epitaxy (MOMBE) have been used for optimization of specific layers. For details on these techniques see M. Micovic et al., J. Vac. Sci. Technol. B16 (3), p. 962 (1998), D.L. Plumton et al., Electronic Letters 25 (18), p. 1212 (1989), S.H. Park et al., IEEE Electron Device Lett. 19 (7), p. 118 (1998), D. Zerguine et al., Electronic Letters 29 (15), p. 1349 (1997), F. Alexandre et al., J. Crystal Growth 136, p. 235 (1994), H. Dodo et al, IEEE Electron Device Lett. 19 (4), p. 121 (1998), Y. M. Hsin et al., J. Crystal Growth 188, p. 355 (1998), T. Nomura et al., IEDM, p. 747 (1997), Y-F Yang et al., IEEE Electron Device Lett. 17 (11), p. 531 (1996), and J-H Son et al., Jpn. J. Appl. Phys. 34, p. 1085 (1995). These papers are incorporated herein by references for any essential details of the processing used in the invention. Devices can be fabricated with multi-step regrowth with a minimum overlap of the extrinsic base and subcollector region to reduce C.sub.bc. These regrowth techniques have also been used for the regrowth of the p.sup.+ base contacts to reduce R.sub.b, which, in turn, reduces thermal and shot noise. The techniques used for regrowth each have their advantages. MOMBE, for example, offers the advantage of high doping levels of 3.times.10.sup.19 cm.sup.-3 for Sn, and 7.times.10.sup.19 cm.sup.-3 for C. This technique is also applicable for the growth of InGaAsP quaternary layers, lattice-matched to InP, to grade out the band gap discontinuity at the heterojunctions. MOCVD, on the other hand, offers the advantage of better planarization and step coverage, since the growth temperature and chamber pressure are higher, the reactant species can migrate long distances. MOCVD, MOMBE, and chemical beam epitaxy (CBE) growth techniques allow for selective area growth, since, for epitaxial growth, they require pyrolysis of the source material on the surface.
One problem with the regrowth technique is the production and protection of alignment marks to be used during patterning of the various layers in the base-emitter stack. Since growth occurs on the entire wafer, and the lateral growth rate is dependent on the crystallographic direction, any initial alignment marks formed e.g. at the sub-collector level become distorted during later growth and processing. To date, these structures have been made using contact alignment. However, this gives registration capability of 1 micron or more. Dense devices arrays and state of the art OICs require better alignment tolerances.